Publications

Graphene is emerging as an attractive electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. However, the conventional dielectric integration and device fabrication processes cannot be readily applied to graphene transistors because they can often introduce substantial defects into the monolayer of carbon lattices and severely degrade the device performance. Here we describe a new strategy to fabricate high performance graphene transistors through the hetero-integration of graphene with inorganic nanostructures. First, I will describe the fabrication of high mobility top-gated graphene transistors by first synthesizing free-standing high-k oxide nanostructures and then transferring them onto graphene as top-gate dielectrics. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties, and can be used as the top-gate dielectrics to enable graphene transistors with the highest carrier mobility exceeding 20,000 cm2/V•s. Furthermore, we describe a self-aligned approach using a metal-dielectric core-shell nanowire as the top-gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. This fabrication approach preserves the high carrier mobility in graphene, and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords unprecedented transistor performance with the projected intrinsic cut-off frequency approaching terahertz regime.